OS202
Binding Memory Addres Address binding is the process of mapping from one address space to another address space.
Compile time If you know what compile time where the process will reside in memory, then absolute code can be generated. If, at some later time, the starting location changes, then it will be necessary to recompile this code. Load time If it is not known at compile time where the process will reside in memory, then the compiler must generate relocatable code. If the starting address changes, we need only reload the user code to incorporate this changed value. Execution time If the process can be moved during its execution fromone memory segment to another, then binding must be delayed until run time. Special hardware must be available for this scheme to work
Logical Address vs Pyhsical Address Space
An address generated by the CPU is commonly referred to as a logical address,
whereas an address seen by the memory unit—that is, the one loaded into
the memory-address register of the memory—is commonly referred to as a physical address.
Memory Management Unit (MMU)
A memory management unit (MMU) is a computer hardware component that handles all memory and caching operations associated with the processor.
In other words, the MMU is responsible for all aspects of memory management. It is usually integrated into the processor
although in some systems it occupies a separate IC (integrated circuit) chip.
Paging
Paging is a memory management scheme that permits a process’s physical address space to be non-contiguous.
Paging avoids external fragmentation and the associated need for compaction, two problems that plague contiguous memory allocation.
Transition Look Aside Buffer (TLB)
The TLB is associative, high-speed memory. Each entry in the TLB consists of two parts: a key (or tag) and a value.
When the associative memory is presented with an item, the item is compared with all keys simultaneously.
Implement Paging
The basic method for implementing paging involves breaking physical memory into fixed-sized blocks called frames and breaking logical memory into
blocks of the same size called pages.
Hierarchical Paging Because of the enourmous size of page table, we would not want to allocate all of the in the main memory One simple solution to this problemis to divide the page table into smaller pieces. Hashed Page Tables One approach for handling address spaces larger than 32bits is to use a hashed page table with the hash value being the virtual page number. Each entry in the hash table contains a linked list of elements that hash to the same location (to handle collisions). Inverted Page Tables Since Operating System need to translate virtual address into physical address, this operation consume many memory. Therefore, we can use inverted page table to solve this problem.
Oracle SPARC Solaris
Solaris running on the SPARC CPU is a fully 64-bit operating system and as such has to solve
the problem of virtual memory without using up all of its physical memory by keeping multiple levels of page tables.
Its approach is a bit complex but solves the problem eficiently using hashed page tables.